In known data processing systems, various circuit modules are coupled to a central communication bus for communicating operands between the circuit modules. To avoid communication bus conflicts and data collisions, a bus master is acknowledged in the system. The bus master typically is given exclusive use privileges of the communication bus. Therefore, an arbitration mechanism exists for establishing a bus priority and implementing the priority. Typical bus mastership arbitration between a plurality of masters on a computer communication bus use a simple priority scheme or a round robin priority which provides an exclusive portion of the bus bandwidth to the various bus masters. A central processing unit (CPU) typically has the lowest priority in a system due to: (1) the CPU's ability to utilize the majority of bus bandwidth itself; (2) the CPU's ability to control the other bus masters; and (3) an assumption that the operations of the other bus masters which perform specialized functions are more important to the required system operation. However, in an interrupt driven system, there are instances wherein the CPU may need to increase its priority as compared with the other bus masters. As an example, consider a situation wherein a CPU receives a high priority interrupt request from a peripheral circuit module requiring immediate servicing. Such a situation may occur should a storage register begin to reach capacity or overflow. However, if the interrupt occurs when a direct memory access (DMA) controller is performing a long DMA block transfer of operands, the DMA is typically allowed to finish the currently executing operation in accordance with an established bus master priorization. As a result, the CPU may not be able to adequately service the interrupt. Other systems have attempted to limit DMA bus bandwidth utilization or have given all interrupts top priority within a system in order to balance the required needs of DMA bus mastership and interrupt service. However, such systems are not very application flexible and do not generally accommodate interrupts of varying importance.